1. Field of the Invention
The present invention relates to a memory device comprising an array of memory cells, and a method of operation of such a memory device, and in particular to a technique for determining when a write operation has completed within the addressed memory cells of the memory device.
2. Description of the Prior Art
As process geometries shrink in modern data processing systems, the variability in the operating characteristics of the individual circuit elements increases. Considering as an example a memory device consisting of an array of memory cells, it will be understood that each memory cell will typically consist of a number of electronic components such as transistors, and the variability in those individual components significantly increases as process geometries shrink. Furthermore, there is an increasing desire to operate data processing systems at lower and lower supply voltages, and as the supply voltage decreases, reliability issues due to the variations in the individual components become more prominent.
In order to ensure correct operation of a memory, memory system designers normally operate the memory system to ensure that when a write operation is performed, the addressed memory cells remain enabled, and the write data remains asserted, for a period of time sufficient to ensure that all of the addressed memory cells will have updated their internal state to correctly reflect the write data before the write operation is terminated, and in particular the period of time allowed for completion of the write operation is chosen having regard to a worst case set of assumptions surrounding manufacturing variation, ambient conditions, etc associated with the memory system concerned. Hence, a memory system designer will calculate a slowest likely write speed and then add a certain safety margin to this when deciding at what speed the memory should be operated. Whilst this approach is safe in terms of ensuring correct operation and data integrity, it can significantly limit the data processing performance that may be achieved.
Furthermore, given the increase in variability of components that occurs as process geometries shrink, this will then lead to larger margins needing to be specified in order to ensure correct operation.
Traditionally, many of the techniques for controlling the timing of a write operation have been derived from techniques used to control the timing of a read operation within the memory cell. When considering a read operation, sense amplifiers connected to the various bit lines are arranged to sample the voltages on those bit lines when triggered to do so by a sense amplifier enable signal. Various techniques have been developed for determining when to generate such a sense amplifier enable signal, for example by using self-timed read paths. Commonly owned U.S. Pat. No. 7,339,842 describes one such self-timed read path technique for generating a sense amplifier enable signal.
One known technique for controlling the timing of a write operation is to use the signal generated by the self-timed read path to act as a termination signal for the write operation. Traditionally, such an approach has been acceptable since it was typically the case that the timing of read operations was more critical, as these typically took longer than write operations and hence were performance limiting. By the time a termination signal was generated by the self-timed read path, it could be ensured that the write operation would have completed. However, as process geometries shrink in modem data processing systems, the performance of write operations is becoming more critical, and indeed write operations can in fact take longer than read operations. One known enhancement to the above approach (employed for example by ARM Limited of Cambridge, United Kingdom) is to use the self-timed read path for timing of write operations, and thus assume by default that the write time is equal to the read time, but to then optionally extend the write time with varying delay elements set/programmed by external pins (either at SoC design time or dynamically). This can hence accommodate situations where write operations take longer than read operations. However, the approach still has the disadvantage that it tracks write timing based on a self-timed read path. Accordingly, there is a need to find improved techniques for tracking the time taken for write operations to complete.
The article “Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays”, by Arijit Raychowdhury et al, IEEE Journal of Solid-State Circuits, Volume 46, No. 4, April 2011, page 797 to 805, describes a design of tunable replica bits (TRBs) used to alleviate a significant portion of the Vcc guardband within a memory array based on 8T SRAM cells. Tunable replica bits are described for both read operations and write operations. However, the described design employs a single bit cell as the replica cell, and in practice this can give rise to a large degree of variability in the circuit, reducing accuracy. In addition, the single bit cell replica cell is tuned using an external voltage, which requires the provision of extra reference voltages to the circuit. Furthermore, such an approach does not capture the true characteristics of a write operation, since it is not based on mimicking the activities that actually occur within the individual bit cells of the memory array. In particular, when considering the operations that occur at the bit cell level, consideration has to be given to the analogue effects that occur due to the flipping of state within the individual bit cells, for example the dependence on threshold voltage Vt and current strength of each device, as well as the feedback loop which directly enables and fights the change of state required during a write operation. In addition, the approach described in the paper would need to be optimised for any particular memory instance, and hence does not provide a solution that provides the required flexibility for adoption within the memory compiler space. Other problems with this prior art approach is that the described technique focuses on determining read and write Vmin based on a process monitor type circuit having some bitcells in it, but it does not focus on tracking timing in a real memory device, and does not have any mechanism for observing real path effects in a memory device. In addition the approach adds a significant area overhead in order to support dynamic tuning.
Accordingly, it would be desirable to provide an improved technique for increasing the performance of write operations within a memory device.